Metal-oxide-semiconductor (MOS) technology is a commonly-used technology for fabricating field effect transistors (FETs) as part of advanced integrated circuits, such as CPUs, memory, and storage devices, and the like. In MOS technology, a FET may be formed by depositing a gate structure over a channel region connecting a source and a drain. In order to improve device performance, particularly to reduce parasitic device capacitance, FETs may be fabricated on a semiconductor-on-insulator (SOI) substrate. An SOI substrate may contain a base substrate layer, a buried insulator (BOX) layer above the base substrate layer, and a top semiconductor layer above the BOX layer. FETs formed on an SOI substrate have channel regions formed in the top semiconductor layer of the SOI substrate. Further, FETs formed on extremely-thin SOI (ETSOI) substrates (i.e., SOI substrates with top semiconductor layers having a thickness of generally less than approximately 20 nm) may further benefit from superior short channel control and device matching.
As FETs continue to become smaller in size, carrier mobility in the channel region may also be reduced due in part to increased dopant concentration and, therefore channel strain may be necessary to achieve desired device performance. However, it may be difficult to apply compressive strain to the channel region of pFETs (i.e., FETs with p-type doped channel regions) formed on ETSOI substrates due to the relative thinness of the top semiconductor layers of the ETSOI substrates. Commonly used compressive strain techniques, such as stress liners and embedded silicon-germanium source/drain regions may prove ineffective when applied to ETSOI pFETs. Therefore, a new method of applying compressive stress to ETSOI pFETs may be desirable.